The present invention relates generally to electronic design automation and computer-aided hardware design. In particular, it is a computer-based technique for compiling functional algorithmic descriptions written in a high-level software language into digital hardware implementations.
Current digital hardware design is done using hardware description languages (HDLs) such as Verilog and VHDL. These languages provide special constructs to handle the description of digital hardware-specific entities such as registers and clocks. While these languages are effective in describing hardware circuits they provide little in the way of high level abstractions to manage the complexity of modern designs. In contrast, modern software languages, and in particular object-oriented software languages such as Java and C++ provide robust high-level constructs that are very effective at managing complexity and serve to improve designer productivity as well as design quality.
In order for designers to keep pace with the amount of resources available in digital integrated circuits, designers must be prepared to double their productivity every 18 months. This is because the amount of available silicon doubles every 18 months. Current approaches to improving designer productivity using HDLs have had only limited success. The key to overcoming this challenge is to leverage high-level software languages for the design of hardware. However, a number of obstacles are readily apparent. Software languages were not designed for the description of hardware, and as such have no constructs for handling hardware specific structures. In addition, the underlying assumptions inherent in a software program (sequential execution, availability of a stack and heap) are not necessarily valid or desirable in a hardware implementation.
These challenges have, in the past, largely been addressed by either working to extend current HDLs to provide higher level construct or by adding features to a high-level software language to describe hardware specific constructs. However, neither approach has resulted in acceptable results. Extending an HDL is simply a stop-gap measure that cannot scale and does not solve the problem for the long term. Adding features to an existing software language to describe hardware seems like a reasonable approach, but what then happens is that the higher level of abstraction is lost, and the language simply turns into another syntax that implements the same HDL semantics.
The invention addresses the compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s). This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.